The present invention relates generally to integrated circuits (ICs) and more specifically to memory circuits that support multiple memory modes.
Random access memory (RAM) and non-volatile memory like read-only memory (ROM) are used in a wide array of applications. Memory blocks or memory circuits in an integrated circuit device can be configured differently, i.e. either as a RAM or a ROM, based on a user's application. For instance, SRAM memory cells can be configured as ROM and be loaded with values during configuration of the integrated circuit device. These memory cells can then be configured to operate in read only mode during post-configuration operation of the device.
In some devices where the extra control circuitry needed to properly configure an SRAM as a ROM is removed, a programmable switch may be placed in between back-to-back inverters in the SRAM cell. During ROM mode, the switch could be connected either to a power supply or to a ground potential to force the SRAM cell to a fixed value. In RAM mode, the switch could complete the back-to-back connection of the SRAM cell. However, using a switch this way contributes to extra capacitance and resistance loading on one side of the SRAM cell that can potentially degrade the read and write margin of the SRAM cell. Consequently, the SRAM cell becomes more susceptible to noise and loading mismatch.
Therefore, it is advantageous to have a memory cell that can support both RAM and ROM modes and still improve, or at least not degrade, the read and write margin. It is also advantageous to have a memory cell that reduces current leakage in a reduced power consumption mode such as standby mode. It is further advantageous to have a substantially symmetrical memory circuit in order to reduce mismatch loading in the memory circuit and improve layout matching.